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dc to 2.0 ghz multiplier adl5391 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features ultrafast symmetric multiplier function: v w = (v x v y )/1 v + v z unique design ensures absolute xy-symmetry identical x and y amplitude/timing responses adjustable gain scaling, dc-coupled throughout, 3 db bandwidth of 2 ghz fully differential inputs, may be used single ended low noise, high linearity accurate, temperature stable gain scaling single-supply operation (4.5 v to 5.5 v @ 130 ma) low current power-down mode 16-lead lfcsp applications wideband multiplication and summing high frequency analog modulation adaptive antennas (diversity/phased array) square-law detectors and true rms detectors accurate polynomial function synthesis dc capable vga with very fast control functional block diagram 06059-001 ymns ypls gadj zmns zpls wpls wmns xpls xmns vmid enbl comm vpos w = xy/1v+z adl5391 figure 1. general description the adl5391 draws on three decades of experience in advanced analog multiplier products. it provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis. v w = ( v x v y )/ 1 v + v z the most significant advance in the adl5391 is the use of a new multiplier core architecture, which differs markedly from the conventional form that has been in use since 1970. the conventional structure that employs a current mode, translinear core is fundamentally asymmetric with respect to the x and y inputs, leading to relative amplitude and timing misalignments that are problematic at high frequencies. the new multiplier core eliminates these misalignments by offering symmetric signal paths for both x and y inputs. the z input allows a signal to be added directly to the output. this can be used to cancel a carrier or to apply a static offset voltage. the fully differential x, y, and z input interfaces are operational over a 2 v range, and they can be used in single-ended fashion. the user can apply a common mode at these inputs to vary from the internally set v pos /2 down to ground. if these inputs are ac-coupled, their nominal voltage will be v pos /2. these input interfaces each present a differential 500 input impedance up to approximately 700 mhz, decreasing to 50 at 2 ghz. the gain scaling input, gadj, can be used for fine adjustment of the gain scaling constant () about unity. the differential output can swing 2 v about the v pos /2 common-mode and can be taken in a single-ended fashion as well. the output common mode is designed to interface directly to the inputs of another adl5391. light dc loads can be ground referenced; however, ac-coupling of the outputs is recommended for heavy loads. the enbl pin allows the adl5391 to be disabled quickly to a standby mode. it operates off supply voltages from 4.5 v to 5.5 v while consuming approximately 130 ma. the adl5391 is fabricated on analog devices proprietary, high performance, 65 ghz, soi complementary, sige bipolar ic process. it is available in a 16-lead, pb-free, lfcsp and operates over a ?40c to +85c temperature range. evaluation boards are available.
adl5391 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ..............................................7 general description ....................................................................... 10 basic theory ............................................................................... 10 basic connections ...................................................................... 10 evaluation board ............................................................................ 13 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 7/06revision 0: initial version
adl5391 rev. 0 | page 3 of 16 specifications v pos = 5 v, t a = 25c, z l = 50 differential, zpls = zmns = open, gadj = open, unless otherwise noted. transfer function: w = xy/1 v + z, common mode internally set to 2.5 v nominal. table 1. parameter conditions min typ max unit multiplicand inputs (x, y) xpls, xmns, ypls, ymns differential voltage range differential, common mode = 2.5 v 2 v p-p common-mode range for full differential range 0 2.5 v input offset voltage dc 20 mv vs. temperature ?40c to +85c 20 mv differential input impedance f = dc 500 f = 2 ghz 150 fundamental feedthrough, x or y f = 50 mhz, x (y) = 0 v, y (x) = 0 dbm, relative to condition where x (y) = 1 v ?42 db f = 1 ghz ?35 db gain x = 50 mhz and 0 dbm, y = 1 v 0.5 db x = 1 ghz and 0 dbm, y = 1 v ?1.33 db dc linearity x to output, y = 1 v 1 % fs scale factor x = y = 1 v 1 v/v cmrr 1 v p-p, y = 1 v, f = 50 mhz 42.1 db summing input (z) zpls, zmns differential voltage range common mode from 2.5 v down to comm 2 v p-p common-mode range for full differential range 0 2.5 v gain from z to w, f 10 mhz, 0 dbm, x = y = 1 v 0.1 db differential input impedance f = dc 500 f = 2 ghz 150 outputs (w) wpls, wmns differential voltage range no external common mode 2 v common-mode output v pos ? 2.5 v output noise floor x = y = 1 v dc f = 1 mhz ?133 dbm/hz f = 1 ghz ?133 dbm/hz x = y = 0 f = 1 mhz ?138 dbm/hz f = 1 ghz ?138 dbm/hz output noise voltage spectral density x = y = 0, f = 1 mhz 26.7 nv/hz output offset voltage z = 0 v differential 19 mv vs. temperature 19 mv differential output impedance f = dc 0 f = 200 mhz 75 f = 2 ghz 500 dynamic characteristics frequency range x, y, z to w 0 2 ghz slew rate w from ?2.0 v to +2.0 v, 150 8800 v/s settling time x stepped from ?1 v to +1 v, z = 0 v, 150 2.1 ns second harmonic distortion x (y) = 0 dbm, y (x) = 1 v, fund = 10 mhz ?60 dbc fund = 200 mhz ?51 dbc third harmonic distortion x (y) = 0 dbm, y (x) = 1 v, fund = 10 mhz ?61.5 dbc fund = 200 mhz ?51.6 dbc
adl5391 rev. 0 | page 4 of 16 parameter conditions min typ max unit oip3 two-tone ip3 test; x (y) = 100 mv p-p/tone (?10 dbm into 50 ), y (x) = 1 f1= 49 mhz, f = 50 mhz 26.5 dbm f1 = 999 mhz, f2 = 1 ghz 14 dbm oip2 f1 = 49 mhz, f = 50 mhz 45.5 dbm f1 = 999 mhz, f2 = 1 ghz 28 dbm output 1 db compression point x (y) to w, y (x) = 1 v, 50 mhz 15.1 dbm 1 ghz 13.2 dbm group delay 200 mhz 0.5 ns 1 ghz 0.7 ns differential gain error, x/y f = 3.58 mhz 2.7 % differential phase error, x/y f = 3.58 mhz 0.23 degrees gain trimming () gadj nominal bias unconnected 1.12 v input range 0 2 v gain adjust range input 0 v to 2 v 9.5 db reference voltage vmid v pos /2 v source current common-mode for x, y, z = 2.5 v 50 ma power and enable v pos , comm, enbl supply voltage range 4.5 5.5 v total supply current common-mode for x, y, z = 2.5 v 135 ma disable current enbl = 0 v 7.5 ma disable threshold high to low 1.5 v enable response time delay following high-to-low transition until device meets full specifications 150 ns disable response time delay following low-to-high transition until device produces full attenuation 50 ns
adl5391 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltage v pos 5.5 v enbl 5.5 v xpls, xmns, ypls, ymns, zpls, zmns v pos gadj v pos internal power dissipation 800 mw ja (with pad soldered to board) 73c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adl5391 rev. 0 | page 6 of 16 pin configuration and fu nction descriptions 06059-002 pin 1 indicator 1 comm 2 vpos 3 vpos 4 vpos 11 ypls 12 ymns 10 zpls 9zmns 5 w p l s 6 w m n s 7 c o m m 8 g a d j 1 5 e n b l 1 6 v m i d 1 4 x m n s 1 3 x p l s adl5391 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 7 comm device common. connect via lowest possible impedance to external circuit common. 2 to 4 v pos positive supply voltage. 4.5 v to 5.5 v. 5, 6 wpls, wmns differential outputs. 8 gadj denominator scaling input. 9, 10 zmns, zpls differential intercept inputs. must be ac-coupled. differential impedance 50 nominal. 11, 12 ypls, ymns differential x-multiplicand inputs. 13, 14 xpls, xmns differential y-multiplicand inputs. 15 enbl chip enable. high to enable. 16 vmid v pos /2 reference output. connect decoupling capacitor to circuit common.
adl5391 rev. 0 | page 7 of 16 typical performance characteristics gadj = open. 3.0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 w diff ( v dc ) x diff (v dc ) y = ?2 y = ?1 y = 0 y = +1 y = +2 06059-007 figure 3. full range dc cross plots 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 w diff ( v dc ) x diff (v dc ) y = ?2 y = ?1 y = 0 y = +1 y = +2 06059-008 figure 4. magnified dc cross plots 2.5 2.0 1.5 1.0 0.5 0 ?1.0 2.0 1.5 1.0 0.5 0 ?0.5 gain (v/v) gadj (v dc ) 06059-009 figure 5. gain vs. gadj (x = y = 1) 14 ?14 200 ?200 ?150 ?100 ?50 ?0 50 100 150 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 2000 1910 1810 1720 1620 1530 1430 1340 1240 1150 1050 955 860 765 670 575 480 385 290 195 100 5 gain (db) phase (degrees) frequency (mhz) 06059-010 figure 6. gain and phase vs. frequency of x swept and y = 1 v, z = 0 v, p in = 0 dbm 4 ?4 ?3 ?2 ?1 0 1 3 2 200 ?200 ?150 ?100 ?50 ?0 50 100 150 1200 1300 1100 990 880 700 660 550 440 330 220 110 1 gain (db) phase (degrees) frequency (mhz) 06059-011 figure 7. gain and phase vs. frequency of z inputs, x = 0 v, y = 0 v, p in = 0 dbm 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 24.5 33.5 32.5 31.5 30.5 29.5 28.5 27.5 26.5 25.5 w output (v) time (ns) x input = 1.0v p-p, @ 200mhz y input = 1.0v dc differential 06059-013 figure 8. large signal pulse response
adl5391 rev. 0 | page 8 of 16 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 24.5 32.5 31.5 30.5 29.5 28.5 27.5 26.5 25.5 w output (v) time (ns) x input = 100mv p-p, @ 200mhz y input = 1.0v dc differential 06059-014 figure 9. small signal pulse response 06059-094 200mhz 400mhz 600mhz 10mhz 30mhz 20mhz 10dbm/div 10dbm/div figure 10. harmonic distortion at 10 mhz and 200 mhz; 0 dbm input to x (y) channels 28 26 24 22 20 18 16 14 12 10 ?40?151035608 average v offset ( 5 v dc ) temperature (c) 06059-015 figure 11. x ( y) offset drift vs. temperature 30 0 5 10 15 20 25 02 y = 1 y = 0.5 1500 1000 500 oip3 (dbm) frequency (mhz) 0 0 0 06059-016 figure 12. oip3 vs. frequency pin 0 dbm, y = 1 v dc, 0.5 v dc 0.05 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.05 0.050.040.030.020.01 0 ?0.01 ?0.02 ?0.03 ?0.04 w diff ( v dc ) y diff (v dc ) +85c, x = +1 +85c, x = ?1 ?40c, x = ?1 ?40c, x = +1 +25c, x = ?1 +25c, x = +1 06059-021 figure 13. z (w) offset over temperature 45 15 20 25 30 35 40 2000 200 400 600 800 1000 1200 1400 1600 1800 snd (nv/ hz) frequency (mhz) x = 0v, y = 1v x = y = 1v x = y = 0v 06059-019 figure 14. noise vs. frequency
adl5391 rev. 0 | page 9 of 16 1.00ufs 3001.000 s11 diff 1.000 201.000 0.654 u ?36.340 deg 1001.000 0.594 u ?92.533 deg 1901.000 0.531 u ?94.448 deg 201.000 0.800 u ?17.218 deg 2001.000 0.564 u ?58.167 deg 06059-017 s11 se figure 15. input s11 1.00ufs 3001.000 1.000 201.000 0.947 u +170.736 deg 1001.000 0.569 u +58.257 deg 1901.000 0.597 u ?69.673 deg 201.000 0.905 u +157.308 deg 2001.000 0.663 u ?39.468 deg 06059-018 s22 diff s22 se figure 16. output s22
adl5391 rev. 0 | page 10 of 16 general description basic theory the multiplication of two analog variables is a fundamental signal processing function that has been around for decades. by convention, the desired transfer function is given by w = xy / u + z (1) where: x and y are the multiplicands. u is the multiplier scaling factor. is the multiplier gain. w is the product output. z is a summing input. all the variables and the scaling factor have the dimension of volts. in the past, analog multipliers, such as the ad835 , were implemented almost exclusively with a gilbert cell topology or a close derivative. the inherently asymmetric signal paths for x and y inevitably create amplitude and delay imbalances between x and y. in the adl5391, the novel multiplier core provides absolute symmetry between x and y, minimizing scaling and phasing differences inherent in the gilbert cell. the simplified block diagram of the adl5391 shows a main multiplier cell that receives inputs x and y and a second multiplier cell in the feedback path around an integrating buffer. the inputs to this feedback multiplier are the difference of the output signal and the summing input, w ? z, and the internal scaling reference, u. at dc, the integrating buffer ensures that the output of both multipliers is exactly 0, therefore ( w ? z ) xu = xy , or w = xy / u + z (2) by using a feedback multiplier that is identical to the main multiplier, the scaling is traced back solely to u, which is an accurate reference generated on-chip. as is apparent in equation 2, noise, drift, or distortion that is common to both multipliers is rejected to first-order because the feedback multiplier essentially compensates the impairments generated in the main multiplier. the scaling factor, u, is fixed by design to 1.12 v. however, the multiplier gain, , can be adjusted by driving the gadj pin with a voltage ranging from 0 v to 2 v. if left floating, then = 1 or 0 db, and the overall scaling is simply u = 1 v. for vgadj = 0 v, the gain is lowered by approximately 4 db; for vgadj = 2 v, the gain is raised by approximately 6 db. figure 5 shows the relationship between (v/v) and vgadj. the small-signal bandwidth from the inputs x, y, and z to the output w is a single-pole response. the pole is inversely proportional to . for = 1 (gadj floating), the bandwidth is about 2 ghz; for > 1, the bandwidth is reduced; and for < 1, the bandwidth is increased. all input ports, x, y, and z, are differential and internally biased to midsupply, v pos /2. the differential input impedance is 500 up to 100 mhz, rolling off to 50 at 2 ghz. all inputs can be driven in single-ended fashion and can be ac-coupled. in dc-coupled operation, the inputs can be biased to a common mode that is lower than v pos /2. the bias current flowing out of the input pins to accommodate the lower common mode is subtracted from the 50 ma total available from the internal reference v pos /2 at the vref pin. each input pin presents an equivalent 250 dc resistance to v pos /2. if all six input pins sit 1 v below v pos /2, a total of 6 1 v/250 = 24 ma must flow internally from vref to the input pins. calibration the dc offset of the adl5391 is approximately 20 mv but changes over temperature and has variation from part to part (see figure 4 ). it is generally not of concern unless the adl5391 is operated down to dc (close to the point x = 0 v or y = 0 v), where 0 v is expected on the output (w = 0 v). for example, when the adl5391 is used as a vga and a large amount of attenuation is needed, the maximum attenuation is determined by the input dc offset. applying the proper voltage on the z input removes the w offset. calibration can be accomplished by making the appropriate cross plots and adjusting the z input to remove the offset. additionally, gain scaling can be adjusted by applying a dc voltage to the gadj pin, as shown in figure 5 . basic connections multiplier connections the best adl5391 performance is achieved when the x, y, and z inputs and w output are driven differentially; however, they can be driven single-ended. single-ended-to-differential transformations (or differential-to-single-ended transformations) can be done using a balun or active components, such as the ad8313 , the ad8132 (both with operation down to dc), or the ad8352 (for higher drive capability). if using the adl5391 single-ended without ac coupling capacitors, the reference voltage of 2.5 v needs to be taken into account. voltages above 2.5 v are positive voltages and voltages below 2.5 v are negative voltages. care needs to be taken not to load the adl5391 too heavily, the maximum reference current available is 50 ma.
adl5391 rev. 0 | page 11 of 16 matching the input/output the input and output impedances of the adl5391 change over frequency, making it difficult to match over a broad frequency range (see figure 15 and figure 16 ). the evaluation board is matched for lower frequency operation, and the impedance change at higher frequencies causes the change in gain seen in figure 6 . if desired, the user of the adl5391 can design a matching network to fit their application. wideband voltage-controlled amplifier/amplitude modulator most of the data for the adl5391 was collected by using it as a fast reacting analog vga. either x or y inputs can be used for the rf input (and the other as the very fast analog control), because either input can be used from dc to 2 ghz. there is a linear relationship between the analog control and the output of the multiplier in the vga mode. figure 6 and figure 7 show the dynamic range available in vga mode (without optimizing the dc offsets). the speed of the adl5391 in vga mode allows it to be used as an amplitude modulator. either or both inputs can have modulation or cw applied. am modulation is achieved by feeding cw into x (or y) and adding am modulation to the y (or x) input. squaring and frequency doubling amplitude domain squaring of an input signal, e, is achieved simply by connecting the x and y inputs in parallel to produce an output of e 2 . the input can be single-ended, differential, or through a balun (frequency range and dynamic range can be limited if used single ended). when the input is a sine wave esin(t), a signal squarer behaves as a frequency doubler, because [] () ( t e te 2 ?= 2cos1 2 )sin( 2 ) (3) ideally, when used for squaring and frequency doubling, there is no component of the original signals on the output. because of internal offsets, this is not the case. if equation 3 were rewritten to include theses offsets, it could separate into three output terms (equation 4). [ ] [] [] ? ? ? ? ? ? ? ? +++ =+?+ 2 )sin(2)cos(2 2 )sin( )sin( 2 2 2 e ofst ofsttet e ofstteofstte (4) where: the dc component is ofst 2 + e 2 /2. the input signal bleedthrough is 2esin(t)ofst. the input squared is e 2 /2[cos(2t)]. the dc component of the output is related to the square of both the offset (ofst) and the signal input amplitude (e). the offset can be found in figure 4 and is approximately 20 mv. the second harmonic output grows with the square of the input amplitude, and the signal bleedthrough grows proportionally with the input signal. for smaller signal amplitudes, the signal bleedthrough can be higher than the second harmonic component. as the input amplitude increases, the second harmonic component grows much faster than the signal bleedthrough and becomes the dominant signal at the output. if the x and y inputs are driven too hard, third harmonic components will also increase. for best performance creating harmonics, the adl5391 should be driven differentially. figure 17 shows the performance of the adl5391 when used as a harmonic generator (the evaluation board was used with r9 and r10 removed and r2 = 56.2 ). if dc operation is necessary, the adl5391 can be driven single ended (without the dc blocks). the flatness of the response over a broad frequency range depends on the input/output match. the fundamental bleed through not only depends on the amount of power put into the device but also depends on matching the unused differential input/output to the same impedance as the used input/output. figure 18 shows the performance of the adl5391 when driven single ended (without ac coupling capacitors), and figure 19 shows the schematic of the setup. a resistive input/output match were used to match the input from dc to 1 ghz and the output from dc to 2 ghz. reactive matching can be used for more narrow frequency ranges. when matching the input/output of the adl5391, care needs to be taken not to load the adl5391 too heavily; the maximum reference current available is 50 ma. ? 15 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 10 100 200 300 400 500 600 700 800 900 1000 gain (dbm) frequency (mhz) second harmonic gain bleedthru gain third harmonic gain 06059-026 figure 17. adl5391 used as a harmonic generator
adl5391 rev. 0 | page 12 of 16 0 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 10 100 200 300 400 500 600 700 800 900 1000 gain (dbm) frequency (mhz) bleedthru gain second harmonic gain third harmonic gain 06059-027 figure 18. single-ended (dc) adl5 391 used as a harmonic generator 21? 74? 21? 74? x in yin 150? 62? 5db pad 5db pad 10db pad 53 ? 53? 200? xm xp ym yp wp wm 06059-028 figure 19. setup for single-ended data use as a detector the adl5391 can be used as a square law detector. when amplitude squaring is performed, there are components of the multiplier output that correlate to the signal bleedthrough and second harmonic, as seen in equation 4. however, as noted in the squaring and frequency doubling section, there is also a dc component that is directly related to the offset and the squared input magnitude. if a signal is split and feed into the x and y inputs and a low-pass filter were place on the output, the resulting dc signal would be directly related to the square of the input magnitude. the intercept of the response will shift slightly from part to part (and over temperature) with the offset, but this can be removed through calibration. figure 20 shows the response of the adl5391 as a square law detector, figure 21 shows the error vs. the input power, and figure 22 shows the configuration used. 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 00 0.7 0.6 0.5 0.4 0.3 0.2 0.1 v out (v) v in (v rms) 2 06059-091 . 8 figure 20. adl5391 used as square law de tector dc output vs. square of input 1.6 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?30 10 50 ?5 ?10 ?15 ?20 ?25 error (db) pin x (dbm) 06059-092 figure 21. adl5391used as a square law detector error vs. power input 0 6059-093 t1 45nf 40h 40h 74h 74h j2 wm j1 wp xm xp ym yp 11 12 13 14 wp wm 6 5 r2 56.2 ? tc1-1-13m t3 c7 0.1f c18 0.1f j6 y p r1 56.2 ? tc1-1-13m t2 c4 0.1f c20 0.1f j8 xp r4 100 ? r12 open 40nf r6 24.9 ? r5 24.9 ? figure 22. schematic for adl5391 used as square law detector
adl5391 rev. 0 | page 13 of 16 evaluation board r1 56.2 ? comm vpos vpos vpos wmns gadj zpls zmns wpls comm ymns ypls xmns xpls enbl vmid t1 vpos tp13 tp comm tp12 c10 100pf c12 0.1f 2 3 1 4 5 6 7 8 9 11 12 13 14 15 16 10 c11 4.7f tc1-1-13m r5 24.9 ? r6 24.9 ? r4 100 ? r12 open wp_dc tp1 r7 open wp j1 wm j2 c2 0.1f c5 open c13 open c14 0.1f r11 open r19 0 ? gadj j3 tc1-1-13m r3 zm_dc tp4 zp_dc tp5 r15 0 ? r14 0 ? zm j4 zp j5 c9 open c8 0.1f c17 0.1f t4 c15 open open tp comm tp14 r2 open r10 0 ? r9 0 ? t3 c16 open tc1-1-13m ym_dc tp7 yp_dc tp6 ym j7 yp j6 c7 0.1f c6 open c18 0.1f r16 open r17 open t2 c19 open tc1-1-13m xm_dc tp9 xp_dc tp8 xm j9 xp j8 c4 0.1f c1 open c20 0.1f wm_dc tp2 r13 open 1 3 sw1 c3 0.1f vmid tp11 2 r8 open enbl_dc tp10 enbl j10 r20 0 ? gadj_dc tp3 r18 0 ? 06059-025 adl5391 figure 23. ADL5391-EVALZ evaluation board schematic 06059-030 figure 24. component side metal of evaluation board 0 6059-031 figure 25. component side silkscreen of evaluation board
adl5391 rev. 0 | page 14 of 16 table 4. evaluation board configuration options component function part number default value j1, j5, j6, j8 sma connectors for single-ended, high frequency operation. if j5 and j6 are used, r9, r10, r14, and r15 should be removed. r2 and r3 should also be populated to match the inputs. if used in broadband operation, c4, c7, c8, and c2 need to be replaced with 0 resistors. wp, zp, yp, xp j2, j4, j7, j9 sma connectors for broadband differential operation. if these are used, baluns should be removed and jumped over using 0 resistors, and c14, c15, c18, and c20 should be removed. wm, zm, ym, xm j3 sma connector for connection to gadj. gadj t1, t2, t3, t4 single-ended-to-differential transformation for high frequency ac operation. if dc operation is necessary, the baluns can be removed and jumped over using 0 resistors. tc1-1-13m+ mini-circuits t3 and t4 are populated, but the y and z inputs are set up for dc operation. c2, c4, c7, c8, c14, c17, c18, c20 dc block capacitors. 0.1 f, 0402 capacitors c1, c5, c6, c9, c13, c15, c16, c19 not installed, dc block capacitors. open, 0402 capacitors r9, r10, r14, r15, r18 snubbing resistors. 0 , 0402 resistors r19, r20 snubbing resistors. 0 , 0603 resistors r7, r13, r16, r17 snubbing resistors. open, 0402 resistors c10 filter capacitor. 100 pf, 0402 capacitor c12 filter capacitor. 0.1 f, 0402 capacitor c3 filter capacitor. 0.1 f, 0603 capacitor c11 filter capacitor. 4.7 f, 3216 capacitor r1 matching resistor. 56.2 , 0603 resistor r2, r3, r12 matching resistors. input impedance to x, y, and z inputs are the same. for the same frequency, r1, r2, and r3 should be the same. open, 0603 resistors r5, r6 matching resistor.s 24.9 , 0402 resistors r4 matching resistor. 100 , 0603 resistor r8, r11 can be used for voltage divider or filtering. open, 0603 resistors sw1 enable switch: enable = 5 v, disable = 0 v. sw1 installed tp1, tp2, tp4, tp5, tp6, tp7, tp8, tp9 green test loop. wp_dc, wm_dc, zm_dc, zp_dc, yp_dc, ym_dc, xp_dc, xm_dc tp13 red test loop. v pos tp12, tp14 black test loops. comm tp3, tp10, tp11 yellow test loop s. gadj_dc, enbl_dc, vmid dut adl5391. adl5391acpz
adl5391 rev. 0 | page 15 of 16 outline dimensions 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 26. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-3) dimensions shown in millimeters ordering guide model temperature range package descript ion package option ordering quantity adl5391acpz-r2 1 ?40c to +85c 16-lead lfcsp_vq cp-16-3 250 adl5391acpz-r7 1 ?40c to +85c 16-lead lfcsp_vq cp-16-3 1,500 adl5391acpz-wp 1 ?40c to +85c 16-lead lfcsp_vq cp-16-3 50 ADL5391-EVALZ 1 evaluation board 1 1 z = pb-free part.
adl5391 rev. 0 | page 16 of 16 t notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06059-0-7/06(0) ttt

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